Such a conventional automatic vehicle speed control device is shown in FIG. 4 by a block diagram.
The automatic vehicle speed control device A comprises, as shown in FIG. 4, a controller B, a vehicle speed sensor C for outputting vehicle speed data proportional to an actual vehicle speed, a command switch D for outputting a cruise command signal, and an actuator F for driving a throttle valve E in its opening and closing directions. The controller B comprises a microcomputer, a drive circuit H for driving the actuator F by a common signal of the microcomputer G, a constant-voltage circuit I for supplying a predetermined voltage to the microcomputer G and a monitor circuit J for monitoring an operating condition of the microcomputer G by watch dog pulse signals having a constant period T.sub.0 outputter from the microcomputer G and for placing the drive circuit H in a non-operated condition during abnormal, operation of the microcomputer. In FIG. 4, references K and L are a power supply source and a main switch.
The microcomputer G comprises a vehicle speed memory means for storing vehicle speed data of the vehicle speed sensor C upon operation of the command switch D, a control means for supplying a command to the drive circuit H based on the difference between the actual vehicle speed and the stored vehicle speed, and a signal oscillating means for outputting watch dog pulse signals having a constant period T.sub.0 at normal operating.
As shown in FIG. 5, the monitor circuit J comprises a capacitor C101 being charged through a resistor R101 by a watch dog pulse signal "1" outputted from the microcomputer G and being discharged by a watch dog pulse signal "0" through a diode D101 and a resistor R102, and an operational amplifier OP101 having a non-inverted input (+) receiving a voltage of the capacitor C101 through a resistor R103 and an inverted input (-) receiving a reference voltage divided by resistors R104 and R105, and for generating an output signal converted from a level "0" to a level "1" when the voltage level at the non-inverted input (+) is more than the voltage level at the inverted input (-).
The automatic vehicle speed control device A operates as follows. The command switch D is at first in an On condition and then in an OFF condition. The actual vehicle speed at the above OFF condition is stored in the vehicle speed memory means provided in the microcomputer G. The control means provided in the microcomputer G compares a current or present vehicle speed with the stored vehicle speed of the vehicle speed memory means, operates the actuator F by the drive circuit H in accordance with the compared result (difference) and adjusts the opening and closing operation of the throttle valve so as to coincide the actual vehicle speed with the stored vehicle speed, thereby running the vehicle at the desired contact speed.
In such a vehicle speed control, the capacity C101 of the monitor circuit J is repeatedly charge and discharged by the watch dog pulse signals "1" and "0" having constant period T.sub.0 generated from the microcomputer G, the output signal of the operation amplifier OP101 in the monitor circuit J is held at the level "0", and the drive circuit H is operated in accordance with the command signal from the microcomputer G, so that the microcomputer G operates normally. When the microcomputer G is in an abnormal condition from one cause or another and the watch dog pulse signal is held at the level "1", the capacitor C101 of the monitor circuit J is charged at the predetermined voltage and thus the output of the operational amplifier OP101 (that is, "C" shown in FIGS. 4 and 5) becomes the level "1", so that the command of the microcomputer G forbits the drive circuit H from operating, thereby preventing the actuator F from abnormally operating.
In the above conventional automatic vehicle speed control device A, when the microcomputer G is in an abnormal condition and the watch dog pulse signal is held at the level "1" the monitor J may detect this condition. However, as shown in FIG. 6, regardless of abnormal condition of the microcomputer G, there are some cases where the watch dog pulse signal is changed from the level "1" to the level "0" so that at such a condition, there capacitor C101 is held at the discharged condition and thus the abnormal condition of the microcomputer G can not be detected.